EFFICIENT VLSI DESIGN FOR LOW-POWER FFT PROCESSING IN COMMUNICATION SYSTEMS

Abstract

Fast Fourier Transform (FFT) is a cornerstone algorithm in digital communication systems, enabling efficient conversion between time and frequency domains crucial for modulation, demodulation, and spectral analysis. As communication systems advance in speed and complexity, there is growing demand for lowpower VLSI implementations of FFT processors tailored for energy-constrained applications like mobile devices, IoT, and wireless networks. This paper proposes a novel VLSI architecture optimized for low power consumption while maintaining high throughput and compact silicon area. The architecture leverages optimized butterfly computation blocks, pipelined datapaths, and efficient control logic. Implementation results from synthesis and simulation show significant improvements in power and area metrics compared to conventional FFT designs. Experimental analysis details the trade-offs between power, area, and throughput, validating the proposed approach for communication applications. The proposed design offers a practical solution for future energy-efficient communication systems and can be extended to other signal processing tasks.